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Intel(R) LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks. This document also supports the LXT971 device. The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V power supply.
Applications
Combination 10BASE-T/100BASE-TX or 100BASE-FX Network Interface Cards (NICs)

10/100 PCMCIA Cards Cable Modems and Set-Top Boxes
Product Features

3.3V Operation. Low power consumption (300 mW typical). Low-power "Sleep" mode. 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection. MII interface with extended register capability. Robust baseline wander correction performance. 100BASE-FX fiber-optic capable. Standard CSMA/CD or full-duplex operation. Supports JTAG boundary scan.

Configurable via MDIO serial port or hardware control pins. Integrated, programmable LED drivers. 64-ball Plastic Ball Grid Array (PBGA). -- LXT971ABC - Commercial (0 to 70C ambient). -- LXT971ABE - Extended (-40 to 85C ambient). 64-pin Low-profile Quad Flat Package (LQFP). -- LXT971ALC - Commercial (0 to 70C ambient). -- LXT971ALE - Extended (-40 to 85C ambient).
Order Number: 249414-002 August 2002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELAE PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT971A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners.
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Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Contents
1.0 2.0 3.0 Pin Assignments ..............................................................................................................................12 Signal Descriptions ..........................................................................................................................16 Functional Description.....................................................................................................................21 3.1 Introduction .......................................................................................................................21 3.1.1 Comprehensive Functionality .............................................................................21 3.1.2 OSPTM Architecture ............................................................................................21 Network Media / Protocol Support....................................................................................22 3.2.1 10/100 Network Interface ...................................................................................22 3.2.1.1 Twisted-Pair Interface ..........................................................................22 3.2.1.2 Fiber Interface.......................................................................................22 3.2.1.3 Fault Detection and Reporting..............................................................23 3.2.2 MII Data Interface...............................................................................................23 3.2.2.1 Increased MII Drive Strength ...............................................................23 3.2.3 Configuration Management Interface .................................................................24 3.2.3.1 MDIO Management Interface ..............................................................24 3.2.3.2 Hardware Control Interface ..................................................................25 Operating Requirements....................................................................................................26 3.3.1 Power Requirements ...........................................................................................26 3.3.2 Clock Requirements............................................................................................26 3.3.2.1 External Crystal/Oscillator ...................................................................26 3.3.2.2 MDIO Clock .........................................................................................26 Initialization.......................................................................................................................26 3.4.1 MDIO Control Mode ..........................................................................................26 3.4.2 Hardware Control Mode .....................................................................................27 3.4.3 Reduced Power Modes........................................................................................28 3.4.3.1 Hardware Power Down ........................................................................28 3.4.3.2 Software Power Down..........................................................................29 3.4.3.3 Sleep Mode ...........................................................................................29 3.4.4 Reset....................................................................................................................29 3.4.5 Hardware Configuration Settings........................................................................30 Establishing Link...............................................................................................................31 3.5.1 Auto-Negotiation ................................................................................................31 3.5.1.1 Base Page Exchange .............................................................................31 3.5.1.2 Next Page Exchange .............................................................................31 3.5.1.3 Controlling Auto-Negotiation...............................................................31 3.5.2 Parallel Detection ................................................................................................31 MII Operation....................................................................................................................32 3.6.1 MII Clocks ..........................................................................................................32 3.6.2 Transmit Enable ..................................................................................................33 3.6.3 Receive Data Valid .............................................................................................33 3.6.4 Carrier Sense .......................................................................................................33 3.6.5 Error Signals .......................................................................................................33 3.6.6 Collision ..............................................................................................................33 3.6.7 Loopback.............................................................................................................34 3.6.7.1 Operational Loopback ..........................................................................35
3.2
3.3
3.4
3.5
3.6
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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3.7
3.8
3.9
3.10
3.6.7.2 Test Loopback...................................................................................... 35 100 Mbps Operation ......................................................................................................... 36 3.7.1 100BASE-X Network Operations...................................................................... 36 3.7.2 Collision Indication ............................................................................................ 38 3.7.3 100BASE-X Protocol Sublayer Operations ....................................................... 38 3.7.3.1 PCS Sublayer ....................................................................................... 38 3.7.3.2 PMA Sublayer...................................................................................... 41 3.7.3.3 Twisted-Pair PMD Sublayer ................................................................ 42 3.7.3.4 Fiber PMD Sublayer ............................................................................ 43 10 Mbps Operation ........................................................................................................... 43 3.8.1 10BASE-T Preamble Handling.......................................................................... 43 3.8.2 10BASE-T Carrier Sense ................................................................................... 43 3.8.3 10BASE-T Dribble Bits ..................................................................................... 43 3.8.4 10BASE-T Link Integrity Test........................................................................... 44 3.8.4.1 Link Failure.......................................................................................... 44 3.8.5 10BASE-T SQE (Heartbeat) .............................................................................. 44 3.8.6 10BASE-T Jabber .............................................................................................. 44 3.8.7 10BASE-T Polarity Correction .......................................................................... 44 Monitoring Operations ..................................................................................................... 44 3.9.1 Monitoring Auto-Negotiation ............................................................................ 44 3.9.1.1 Monitoring Next Page Exchange......................................................... 45 3.9.2 LED Functions ................................................................................................... 45 3.9.2.1 LED Pulse Stretching........................................................................... 45 Boundary Scan (JTAG1149.1) Functions ........................................................................ 46 3.10.1 Boundary Scan Interface .................................................................................... 46 3.10.2 State Machine..................................................................................................... 46 3.10.3 Instruction Register ............................................................................................ 46 3.10.4 Boundary Scan Register (BSR).......................................................................... 46 Magnetics Information ..................................................................................................... 48 Typical Twisted-Pair Interface ......................................................................................... 48 The Fiber Interface ........................................................................................................... 52 Electrical Parameters ........................................................................................................ 56 Timing Diagrams .............................................................................................................. 61
4.0
Application Information.................................................................................................................. 48 4.1 4.2 4.3
5.0
Test Specifications .......................................................................................................................... 56 5.1 5.2
6.0 7.0 8.0
Register Definitions ........................................................................................................................ 71 Package Specifications.................................................................................................................... 88 Product Ordering Information......................................................................................................... 90
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Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 LXT971A Block Diagram...................................................................................................9 64-Pin PBGA Pin Assignments.........................................................................................10 64-Pin LQFP Pin Assignments..........................................................................................11 Management Interface Read Frame Structure...................................................................21 Management Interface Write Frame Structure ..................................................................21 Interrupt Logic...................................................................................................................22 Initialization Sequence ......................................................................................................24 Hardware Configuration Settings ......................................................................................26 Link Establishment Overview ...........................................................................................28 10BASE-T Clocking .........................................................................................................30 100BASE-X Clocking .......................................................................................................30 Link Down Clock Transition.............................................................................................30 Loopback Paths .................................................................................................................31 100BASE-X Frame Format...............................................................................................32 100BASE-TX Data Path....................................................................................................33 100BASE-TX Reception with no Errors...........................................................................33 100BASE-TX Reception with Invalid Symbol .................................................................33 100BASE-TX Transmission with no Errors......................................................................34 100BASE-TX Transmission with Collision......................................................................34 Protocol Sublayers.............................................................................................................35 LED Pulse Stretching ........................................................................................................42 Typical Twisted-Pair Interface - Switch............................................................................45 Typical Twisted-Pair Interface - NIC................................................................................46 Typical MII Interface ........................................................................................................47 Typical Fiber Interface ......................................................................................................48 100BASE-TX Receive Timing - 4B Mode .......................................................................53 100BASE-TX Transmit Timing - 4B Mode......................................................................54 100BASE-FX Receive Timing..........................................................................................55 100BASE-FX Transmit Timing ........................................................................................56 10BASE-T Receive Timing ..............................................................................................57 10BASE-T Transmit Timing.............................................................................................58 10BASE-T Jabber and Unjabber Timing ..........................................................................59 10BASE-T SQE (Heartbeat) Timing.................................................................................59 Auto Negotiation and Fast Link Pulse Timing..................................................................60 Fast Link Pulse Timing .....................................................................................................60 MDIO Input Timing ..........................................................................................................61 MDIO Output Timing........................................................................................................61 Power-Up Timing..............................................................................................................62 RESET Pulse Width and Recovery Timing ......................................................................62 PHY Identifier Bit Mapping..............................................................................................68 PBGA Package Specification ............................................................................................79 LXT971A LQFP Package Specifications..........................................................................80
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 LQFP Numeric Pin List .................................................................................................... 12 LXT971A MII Signal Descriptions .................................................................................. 14 LXT971A Network Interface Signal Descriptions ........................................................... 15 LXT971A Miscellaneous Signal Descriptions ................................................................. 16 LXT971A Power Supply Signal Descriptions.................................................................. 17 LXT971A JTAG Test Signal Descriptions ...................................................................... 17 LXT971A LED Signal Descriptions ................................................................................ 17 Hardware Configuration Settings ..................................................................................... 26 Carrier Sense, Loopback, and Collision Conditions......................................................... 32 4B/5B Coding ................................................................................................................... 36 BSR Mode of Operation ................................................................................................... 43 Supported JTAG Instructions ........................................................................................... 43 Device ID Register ........................................................................................................... 43 Magnetics Requirements .................................................................................................. 44 I/O Pin Comparison of NIC and Switch RJ-45 Setups..................................................... 44 Absolute Maximum Ratings ............................................................................................. 49 Operating Conditions........................................................................................................ 49 Digital I/O Characteristics 1 ............................................................................................. 50 Digital I/O Characteristics - MII Pins............................................................................... 50 I/O Characteristics - REFCLK/XI and XO Pins............................................................... 50 I/O Characteristics - LED/CFG Pins ................................................................................ 50 100BASE-TX Transceiver Characteristics....................................................................... 51 100BASE-FX Transceiver Characteristics ....................................................................... 51 10BASE-T Transceiver Characteristics............................................................................ 51 10BASE-T Link Integrity Timing Characteristics ........................................................... 52 100BASE-TX Receive Timing Parameters - 4B Mode.................................................... 53 100BASE-TX Transmit Timing Parameters - 4B Mode .................................................. 54 100BASE-FX Receive Timing Parameters ...................................................................... 55 100BASE-FX Transmit Timing Parameters..................................................................... 56 10BASE-T Receive Timing Parameters........................................................................... 57 10BASE-T Transmit Timing Parameters ......................................................................... 58 10BASE-T Jabber and Unjabber Timing Parameters....................................................... 59 10BASE-T SQE Timing Parameters ................................................................................ 59 Auto Negotiation and Fast Link Pulse Timing Parameters .............................................. 60 MDIO Timing Parameters ................................................................................................ 61 Power-Up Timing Parameters .......................................................................................... 62 RESET Pulse Width and Recovery Timing Parameters.................................................. 62 Register Set....................................................................................................................... 63 Register Bit Map............................................................................................................... 64 Control Register (Address 0) ............................................................................................ 66 MII Status Register #1 (Address 1) .................................................................................. 67 PHY Identification Register 1 (Address 2)....................................................................... 68 PHY Identification Register 2 (Address 3)....................................................................... 68 Auto Negotiation Advertisement Register (Address 4).................................................... 69 Auto Negotiation Link Partner Base Page Ability Register (Address 5) ......................... 70 Auto Negotiation Expansion (Address 6)......................................................................... 71 Auto Negotiation Next Page Transmit Register (Address 7) ........................................... 71 Auto Negotiation Link Partner Next Page Receive Register (Address 8)........................ 72 Configuration Register (Address 16, Hex 10) .................................................................. 73
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Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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50 51 52 53 54
Status Register #2 (Address 17) ........................................................................................74 Interrupt Enable Register (Address 18).............................................................................75 Interrupt Status Register (Address 19, Hex 13).................................................................76 LED Configuration Register (Address 20, Hex 14) ..........................................................77 Transmit Control Register (Address 30) ...........................................................................78
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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Revision History
Revision 002 Revision Date: August 6, 2002 Page Description Globally replaced "pseudo-PECL" with Low-Voltage PECL", except when identified with 5 V. 1 12 13 14 16 17 18 19 20 22 23 23 30 35 43 47 47 52 53 54 55 56 56 57 58 58 60 65 72 86 87 90 Front Page: Changed "pseudo-ECL (PECL)" to "Low Voltage PECL (LVPECL). Added "JTAG Boundary Scan" to Product Features on front page. Modified Figure 2 "LXT971A 64-Ball PBGA Assignments" (replaced TEST1 and TEST0 with GND). Modified Figure 3 "LXT971A 64-Pin LQFP Assignments" (replaced TEST1 and TEST0 with GND). Modified Table 1 "LQFP Numeric Pin List" (replaced TEST1 and TEST0 with GND). Added note under Section 2.0, "Signal Descriptions": "Intel recommends that all inputs and multifunction pins be tied to the inactive states and all outputs be left floating, if unused." Modified SD/TP description in Table 3 "LXT971A Network Interface Signal Descriptions". Added Table note 2. Modified Table 4 "LXT971A Miscellaneous Signal Descriptions". Modified Table 5 "LXT971A Power Supply Signal Descriptions". Added Table 8 "LXT971A Pin Types and Modes". Replaced second paragraph under Section 3.2.1.2, "Fiber Interface". Added Section 3.2.2.1, "Increased MII Drive Strength". Changed "Far-End Fault" title to `100BASE-FX Far-End Fault". Modified first sentence under this heading. Modified Figure 8 "Hardware Configuration Settings". Added paragraph after bullets under Section 3.6.7.2, "Test Loopback". Modified text under Section 3.7.3.4, "Fiber PMD Sublayer". Modified Table 13 "Supported JTAG Instructions". Modified Table 14 "Device ID Register". Added a new Section 4.3, "The Fiber Interface". Replaced Figure 25 "Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry". Added Figure 26 "Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry". Added Figure 27 "ON Semiconductor Triple PECL-to-LVPECL Translator". Modified Table 17 "Absolute Maximum Ratings". Modified Table 18 "Operating Conditions": Added Typ values to Vcc current. Modified Table 20 "Digital I/O Characteristics - MII Pins". Modified Table 22 "I/O Characteristics - LED/CFG Pins". Added Table 23 "I/O Characteristics - SD/TP Pin". Added Table 28 "LXT971A Thermal Characteristics". Modified Table 33 "10BASE-T Receive Timing Parameters" Modified Table 42 "Register Bit Map". (Added Table 26 information). Added Table 57 "Digital Config Register (Address 26)". Modified Table 58 "Transmit Control Register (Address 30)". Added Section 8.0, "Product Ordering Information".
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Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Revision 001 Revision Date: January 2001 Page N/A Description Clock Requirements: Modified language under Clock Requirements heading. Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from 40 to 35 and under Max from 60 to 65.
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
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Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Figure 1. LXT971A Block Diagram
RESET ADDR<4:0> MDIO MDC MDINT MDDIS TX_EN TX PCS TXD<3:0> TX_ER TX_CLK Parallel/Serial Converter Management / Mode Select Logic Power Supply Register Set Clock Generator Manchester 10 Encoder Scrambler 100 & Encoder Auto Negotiation Register Set
VCC GND PWRDWN REFCLK TxSLEW<1:0>
OSPTM
Pulse Shaper
TP Driver
+ + JTAG 5 TP/Fiber Out TPFOP TPFON
ECL Driver
LED/CFG<3:1> Collision Detect
OSPTM
Clock Generator Manchester Decoder Media Select Adaptive EQ with Baseline Wander Cancellation 100TX
COL
+ +
100FX TP/Fiber In
TDIO TMS TCK TRST
RX_CLK RXD<3:0> RX PCS RXDV CRS RX_ER Carrier Sense Data Valid Error Detect Serial-toParallel Converter
10
TPFIP TPFIN SD/TP
OSPTM
Slicer
Decoder & 100 Descrambler
+
10BT
-
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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1.0
Pin Assignments
Figure 2. LXT971A 64-Ball PBGA Assignments
1 A MDINT
2 CRS
3 TXD3
4 TXD0
5 RX_ER
6 VCCD
7 RX_DV
8 RXD0 A
B
REF CLK/XI
COL
TXD2
TX_EN
TX_ER
RX_ CLK
N/C
RXD1
B
C
XO
RESET
GND
TXD1
TX_ CLK
GND
N/C
RXD2
C
D
Tx SLEW0
Tx SLEW1
MDDIS
GND
VCCIO
RXD3
N/C
MDIO
D
E
ADDR0
ADDR1
GND
GND
VCCIO
LED/ CFG1
MDC
PWR DWN LED/ CFG3
E
F
ADDR3
ADDR2
GND
GND
TDI
TMS
LED/ CFG2
F
G
ADDR4
SD/TP
VCCA
VCCA
TDO
TCK
GND
GND
G
H
RBIAS 1
TPFOP 2
TPFON 3
TPFIP 4
TPFIN 5
TRST 6
SLEEP 7
PAUSE 8
H
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Datasheet
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Figure 3. LXT971A 64-Pin LQFP Assignments
MDINT CRS COL GND TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK TX_ER RX_ER RX_CLK VCCD GND RX_DV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 REFCLK/XI XO MDDIS RESET TXSLEW0 TXSLEW1 GND VCCIO N/C N/C GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Part # LOT # FPO # LXT971ALC XX XXXXXX XXXXXXXX Rev # 48 RXD0 47 RXD1 46 RXD2 45 RXD3 44 N/C 43 MDC 42 MDIO 41 GND 40 VCCIO 39 PWRDWN 38 LED/CFG1 37 LED/CFG2 36 LED/CFG3 35 GND 34 GND 33 PAUSE
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
RBIAS GND TPFOP TPFON VCCA VCCA TPFIP TPFIN GND SD/TP TDI TDO TMS TCK TRST SLEEP
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Table 1.
LQFP Numeric Pin List
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol REFCLK/XI XO MDDIS RESET TxSLEW0 TxSLEW1 GND VCCIO N/C N/C GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 RBIAS GND TPFOP TPFON VCCA VCCA TPFIP TPFIN GND SD/TP TDI TDO TMS TCK TRST SLEEP PAUSE GND GND LED/CFG3 Type Input Output Input Input Input Input - - - - - Input Input Input Input Input Analog Input - Output Output - - Input Input - Input Input Output Input Input Input Input Input - - I/O Reference for Full Description Table 4 on page 18 Table 4 on page 18 Table 2 on page 16 Table 4 on page 18 Table 4 on page 18 Table 4 on page 18 Table 5 on page 19 Table 5 on page 19 Table 4 on page 18 Table 4 on page 18 Table 5 on page 19 Table 4 on page 18 Table 4 on page 18 Table 4 on page 18 Table 4 on page 18 Table 4 on page 18 Table 4 on page 18 Table 5 on page 19 Table 3 on page 17 Table 3 on page 17 Table 5 on page 19 Table 5 on page 19 Table 3 on page 17 Table 3 on page 17 Table 5 on page 19 Table 3 on page 17 Table 6 on page 19 Table 6 on page 19 Table 6 on page 19 Table 6 on page 19 Table 6 on page 19 Table 4 on page 18 Table 4 on page 18 Table 5 on page 19 Table 5 on page 19 Table 7 on page 19
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Table 1.
LQFP Numeric Pin List (Continued)
Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol LED/CFG2 LED/CFG1 PWRDWN VCCIO GND MDIO MDC N/C RXD3 RXD2 RXD1 RXD0 RX_DV GND VCCD RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 GND COL CRS MDINT Type I/O I/O Input - - I/O Input - Output Output Output Output Output - - Output Output Input Output Input Input Input Input Input - Output Output Open Drain Reference for Full Description Table 7 on page 19 Table 7 on page 19 Table 4 on page 18 Table 5 on page 19 Table 5 on page 19 Table 2 on page 16 Table 2 on page 16 Table 4 on page 18 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 5 on page 19 Table 5 on page 19 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16 Table 5 on page 19 Table 2 on page 16 Table 2 on page 16 Table 2 on page 16
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
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2.0
Note: Table 2.
Signal Descriptions
Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused. LXT971A MII Signal Descriptions
PBGA Pin# LQFP Pin# Symbol Type1 Data Interface Pins A3 B3 C4 A4 B4 C5 D6 C8 B8 A8 A7 A5 B5 B6 60 59 58 57 56 55 45 46 47 48 49 53 54 52 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK RXD3 RXD2 RXD1 RXD0 RX_DV RX_ER TX_ER RX_CLK O O I O Receive Data Valid. The LXT971A asserts this signal when it drives valid data on RXD. This output is synchronous to RX_CLK. Receive Error. Signals a receive error condition has occurred. This output is synchronous to RX_CLK. Transmit Error. Signals a transmit error condition. This signal must be synchronized to TX_CLK. Receive Clock. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps operation. Refer to "Clock Requirements" on page 26 in Section 3.0, "Functional Description". Collision Detected. The LXT971A asserts this output when a collision is detected. This output remains High for the duration of the collision. This signal is asynchronous and is inactive during fullduplex operation. Carrier Sense. During half-duplex operation (Register bit 0.8 = 0), the LXT971A asserts this output when either transmitting or receiving data packets. During full-duplex operation (Register bit 0.8 = 1), CRS is asserted only during receive. CRS assertion is asynchronous with respect to RX_CLK. CRS is de-asserted on loss of carrier, synchronous to RX_CLK. O Receive Data. RXD is a bundle of parallel signals that transition synchronously with respect to the RX_CLK. RXD<0> is the least significant bit. I O Transmit Enable. The MAC asserts this signal when it drives valid data on TXD. This signal must be synchronized to TX_CLK. Transmit Clock. TX_CLK is sourced by the PHY in both 10 and 100 Mbps operations. 2.5 MHz for 10 Mbps operation, 25 MHz for 100 Mbps operation. I Transmit Data. TXD is a bundle of parallel data signals that are driven by the MAC. TXD<3:0> transitions synchronously with respect to the TX_CLK. TXD<0> is the least significant bit. Signal Description
B2
62
COL
O
A2
63
CRS
O
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
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Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Table 2.
LXT971A MII Signal Descriptions (Continued)
PBGA Pin# LQFP Pin# Symbol Type1 Signal Description MII Control Interface Pins Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations. When MDDIS is Low at power-up or reset, the Hardware Control Interface pins control only the initial or "default" values of their respective register bits. After the power-up/reset cycle is complete, bit control reverts to the MDIO serial channel. Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When Register bit 18.1 = 1, an active Low output on this pin indicates status change. Interrupt is cleared by reading Register 19.
D3
3
MDDIS
I
E7 D8 A1
43 42 64
MDC MDIO MDINT
I I/O OD
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain
Table 3.
LXT971A Network Interface Signal Descriptions
PBGA Pin# LQFP Pin# Symbol Type1 Signal Description Twisted-Pair/Fiber Outputs, Positive & Negative. H2 H3 19 20 TPFOP TPFON O During 100BASE-TX or 10BASE-T operation, TPFOP/N pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFOP/N pins produce differential LVPECL outputs for fiber transceivers. Twisted-Pair/Fiber Inputs, Positive & Negative. H4 H5 23 24 TPFIP TPFIN I During 100BASE-TX or 10BASE-T operation, TPFIP/N pins receive differential 100BASE-TX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFIP/N pins receive differential LVPECL inputs from fiber transceivers. Signal Detect2: Dual function input depending on the state of the device. G2 26 SD/TP I Reset and Power-Up. Media mode selection: Tie High for FX mode (Register bit 16.0 = 1) Tie Low for TP mode (Register bit 16.0 = 0) Normal Operation (FX Mode): SD input from the fiber transceiver. Normal Operation (TP Mode): Tie to GND (uses an internal pulldown). 1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain 2. For standard digital loopback testing (Register bit 0.14) in FX mode, the SD pin should be tied to an LVPECL logic High (2.4 V).
Datasheet
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Table 4.
LXT971A Miscellaneous Signal Descriptions
PBGA Pin# LQFP Pin# Symbol Type1 Signal Description Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: D1 D2 5 6 TxSLEW0 TxSLEW1 I TxSLEW1 0 0 1 1 C2 4 16 15 14 13 12 17 33 32 39 1 2 9, 10 44 RESET I TxSLEW0 0 1 0 1 Slew Rate (Rise and Fall Time) 3.0 ns 3.4 ns 3.9 ns 4.4 ns
Reset. This active Low input is OR'ed with the control register Reset bit (Register bit 0.15). The LXT971A reset cycle is extended to 258 s (nominal) after reset is deasserted.
G1 F1 F2 E2 E1 H1 H8 H7 E8 B1 C1 B7, C7 D7
ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 RBIAS PAUSE SLEEP PWRDWN REFCLK/XI XO N/C
I I I I I AI I I I I O -
Address <4:0>. Sets device address.
Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k, 1% resistor. Pause. When set High, the LXT971A advertises Pause capabilities during auto-negotiation. Sleep. When set High, this pin enables the LXT971A to go into a low-power sleep mode. The value of this pin can be overridden by Register bit 16.6 when in managed mode. Power Down. When set High, this pin puts the LXT971A in a power-down mode. Crystal Input and Output. A 25 MHz crystal oscillator circuit can be connected across XI and XO. A clock can also be used at XI. Refer to "Clock Requirements" on page 26 in the Functional Description section. No Connection. These pins are not used and should not be terminated.
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain.
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Table 5.
LXT971A Power Supply Signal Descriptions
PBGA Pin# A6 D4, E3 E4, F3 F4, C6, C3, G7, G8 E5, D5 G3, G4 LQFP Pin# 51 7, 11, 18, 25, 34, 35, 41, 50, 61 8, 40 21, 22 Symbol VCCD Type - Signal Description Digital Power. Requires a 3.3V power supply.
GND
-
Ground.
VCCIO VCCA
- -
MII Power. Requires either a 3.3V or a 2.5V supply. Must be supplied from the same source used to power the MAC on the other side of the MII. Analog Power. Requires a 3.3V power supply.
Table 6.
LXT971A JTAG Test Signal Descriptions
PBGA Pin# F5 G5 F6 G6 H6 LQFP Pin# 27 28 29 30 31 Symbol TDI2 TDO2 TMS2 TCK
2
Type1 I O I I I
Signal Description Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Test clock input sourced by ATE. Test Reset. Test reset input sourced by ATE.
TRST2
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain. 2. If JTAG port is not used, these pins do not need to be terminated.
Table 7.
LXT971A LED Signal Descriptions
PBGA Pin# LQFP Pin# Symbol Type1 Signal Description LED Drivers 1-3. These pins drive LED indicators. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 56 on page 85 for details). Configuration Inputs 1-3. These pins also provide initial configuration settings (refer to Table 9 on page 30 for details).
E6 F7 F8
38 37 36
LED/CFG1 LED/CFG2 LED/CFG3 I/O
1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain. 2. Pull-up/pull-down resistors of 10 k can be implemented if LEDs are used in the design.
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Table 8.
LXT971A Pin Types and Modes
Modes HWReset SFTPWRDN HWPWRDN ISOLATE SLEEP RXD 0-3 DL DL High Z HZ w/ IPLD DL RXDV DL DL High Z HZ w/ IPLD DL Tx/Rx CLKS Output DH Active High Z HZ w/ IPLD DL RXER Output DL DL High Z HZ w/ IPLD DL COL Output DL DL High Z HZ w/ IPLD DL CRS Output DL DL High Z HZ w/ IPLD DL TXD 0-3 Input IPLD IPLD High Z IPLD IPLD TXEN Input IPLD IPLD High Z IPLD IPLD TXER Input IPLD IPLD High Z IPLD IPLD
1. A High Z (High impedance) or three-state determines when the device is drawing a current of less than 20 nA. A High Z with PLD (High impedance with pull-down) state determines when the device is drawing a current of less than 20 A. 2. DL = Driven Low (Logic 0), DH = Driven High (Logic 1), IPLD = Internal Pull-Down (Weak)
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3.0
3.1
Functional Description
Introduction
The LXT971A is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks and complies with all applicable requirements of IEEE 802.3. The LXT971A directly drives either a 100BASE-TX line (up to 140 meters) or a 10BASE-T line (up to 185 meters). The device also supports 100BASE-FX operation via a Low Voltage PECL (LVPECL) interface.
3.1.1
Comprehensive Functionality
The LXT971A provides a standard Media Independent Interface (MII) for 10/100 MACs. The LXT971A performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X standard. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. The LXT971A reads its configuration pins on power-up to check for forced operation settings. If not configured for forced operation, the device uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT971A auto-negotiates with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT971A automatically detects the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and sets its operating conditions accordingly. The LXT971A provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps.
3.1.2
OSPTM Architecture
The LXT971A incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results in improved receiver noise and cross-talk performance. The OSP signal processing scheme also requires substantially less computational logic than traditional DSP-based designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines. This logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT971A provides improved data recovery, EMI performance and low power consumption.
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3.2
Network Media / Protocol Support
The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX).
3.2.1
10/100 Network Interface
The network interface port consists of five external pins (two differential signal pairs and a signal detect pin). The I/O pins are shared between twisted-pair (TP) and fiber. Refer to Figure 3 on page 13 for specific pin assignments. The LXT971A output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output. When not transmitting data, the LXT971A generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface.
3.2.1.1
Twisted-Pair Interface
The LXT971A supports either 100BASE-TX or 10BASE-T connections over 100, Category 5, Unshielded Twisted Pair (UTP) cable. When operating at 100 Mbps, the LXT971A continuously transmits and receives MLT3 symbols. When not transmitting data, the LXT971A generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. Link pulses are transmitted periodically to keep the link up. Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 4 on page 18) allow the designer to match the output waveform to the magnetic characteristics. On the receive side, the internal impedance is high enough that it has no practical effect on the external termination circuit.
3.2.1.2
Fiber Interface
The LXT971A fiber port is designed to interface with common industry-standard fiber modules. It incorporates a Low Voltage PECL interface that complies with the ANSI X3.166 standard for seamless integration. Fiber mode is selected through Register bit 16.0 by the following two methods: 1. Drive the SD input to a value greater than 600 mV during power-up and reset states (all LVPECL signaling levels from a fiber transceiver are acceptable). 2. Configure Register bit 16.0 = 1 through the MDIO interface.
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3.2.1.3
Fault Detection and Reporting
The LXT971A supports two fault detection and reporting mechanisms. "Remote Fault" refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices. It is used only during auto-negotiation, and is applicable only to twisted-pair links. "Far-End Fault" is an optional PMA-layer function that may be embedded within PHY devices. The LXT971A supports both functions (see Section 3.2.1.3.1 and Section 3.2.1.3.2).
3.2.1.3.1
Remote Fault
Register bit 4.13 in the Auto-Negotiation Advertisement Register is reserved for Remote Fault indications. It is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a fault. When the LXT971A receives a Remote Fault indication from its partner during auto-negotiation it does the following:
* Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and * Sets the Remote Fault Register bit 1.4 in the MII Status Register to pass this information to the
local controller.
3.2.1.3.2
100BASE-FX Far-End Fault
The SD/TP pin monitors signal quality during normal operation in fiber mode. If the signal quality degrades beyond the fault threshold, the fiber transceiver reports a signal quality fault condition via the SD/TP pin. Loss of signal quality blocks any fiber data from being received and causes a link loss. If the LXT971A detects a signal fault condition, it can transmit the Far-End Fault Indication (FEFI) over the fiber link. The FEFI consists of 84 consecutive ones followed by a single zero. This pattern must be repeated at least three times. The LXT971A transmits the far-end fault code a minimum of three times if all the following conditions are true:
* * * * 3.2.2
Fiber mode is selected. Fault Code transmission is enabled (Register bit 16.2 = 1). Either Signal Detect indicates no signal or the receive PLL cannot lock. Loopback is not enabled.
MII Data Interface
The LXT971A supports a standard Media Independent Interface (MII). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT971A and a Media Access Controller (MAC). Separate parallel buses are provided for transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set automatically, once the operating conditions of the network link have been determined. Refer to "MII Operation" on page 32 for additional details.
3.2.2.1
Increased MII Drive Strength
A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. The MII drive strength in the LXT971A can be increased by setting Register
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bit 26.11 through software control. Setting Register bit 26.11 = 1 through the MDC/MDIO interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK) to a higher drive strength.
3.2.3
Configuration Management Interface
The LXT971A provides both an MDIO interface and a Hardware Control Interface for device configuration and management.
3.2.3.1
MDIO Management Interface
The LXT971A supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT971A. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 standard. The LXT971A also supports additional registers for expanded functionality. The LXT971A supports multiple internal registers, each of which is 16 bits wide. Specific register bits are referenced using an "X.Y" notation, where X is the register number (0-31) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write operations are disabled and the Hardware Control Interface provides primary configuration control. When MDDIS is Low, the MDIO port is enabled for both read and write operations and the Hardware Control Interface is not used.
3.2.3.1.1
MDIO Addressing
The protocol allows one controller to communicate with multiple LXT971A chips. Pins ADDR<4:0> determine the chip address.
3.2.3.1.2
MDIO Frame Structure
The physical interface consists of a data line (MDIO) and clock line (MDC). The frame structure is shown in Figures 4 and 5 (read and write). MDIO Interface timing is shown in Table 38 on page 69. Figure 4. Management Interface Read Frame Structure
MDC MDIO (Read)
High Z
32 "1"s Preamble
0 ST
1
1
0 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
Z
0
D15 D15D14 D14 D1 Data Read
D1 D0 Idle
Register Address
Turn Around
Write
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Figure 5. Management Interface Write Frame Structure
MDC MDIO (Write)
Idle
32 "1"s Preamble
0 ST
1
0
1 Op Code
A4
A3 PHY Address
A0
R4
R3
R0
1
0 Turn Around
D15
D14 Data
D1
D0 Idle
Register Address Write
3.2.3.1.3
MII Interrupts
The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 6. The LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1, enables the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT971A. Interrupts may be caused by four conditions:
* * * *
3.2.3.2
Auto-negotiation complete Speed status change Duplex status change Link status change
Hardware Control Interface
The LXT971A provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins to set device configuration. Refer to the Hardware Configuration Settings section on page 30 for additional details.
Figure 6. Interrupt Logic
Even X Mask Reg
AND
Even X Status Reg
OR NAND
Interrupt Pin (MDINT)
Force Interrupt
Interrupt Enable
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3.3
3.3.1
Operating Requirements
Power Requirements
The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a single source. Each supply input must be de-coupled to ground. An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or +3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the other side of the MII interface. Refer to Table 20 on page 57 for MII I/O characteristics. As a matter of good practice, these supplies should be as clean as possible.
3.3.2
3.3.2.1
Clock Requirements
External Crystal/Oscillator
The LXT971A requires a reference clock input that is used to generate transmit signals and recover receive signals. It may be provided by either of two methods: by connecting a crystal across the oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the LXT971A/972A Design and Layout Guide for a list of recommended clock sources. A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a crystal, is frequently used in switch applications. Refer to Table 21 on page 57 for clock timing requirements.
3.3.2.2
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock (MDC) speed is a maximum of 8 MHz. Refer to Table 38 on page 69 for details.
3.4
Initialization
When the LXT971A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 7.
3.4.1
MDIO Control Mode
In the MDIO Control mode, the LXT971A reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface.
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3.4.2
Hardware Control Mode
In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control:
* Force network link to 100FX (Fiber). * Force network link operation to:
-- 100BASE-TX, Full-Duplex. -- 100BASE-TX, Half-Duplex. -- 10BASE-T, Full-Duplex. -- 10BASE-T, Half-Duplex.
* Allow auto-negotiation/parallel-detection.
When the network link is forced to a specific configuration, the LXT971A immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT971A begins the auto-negotiation/parallel-detection operation.
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Figure 7. Initialization Sequence
Power-up or Reset Read H/W Control Interface
Initialize MDIO Registers
MDIO Control Mode
Low
MDDIS Voltage Level?
Hardware Control Mode
High
MDIO Controlled Operation (MDIO Writes Enabled)
Disable MDIO Read and Write Operations
Software Reset?
Yes
No
Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset
3.4.3
Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
3.4.3.1
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true:
* * * *
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The LXT971A network port and clock are shut down. All outputs are three-stated. All weak pad pull-up and pull-down resistors are disabled. The MDIO registers are not accessible.
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3.4.3.2
Software Power Down
Software power-down control is provided by Register bit 0.11 in the Control Register (refer to Table 43 on page 74). During soft power-down, the following conditions are true:
* The network port is shut down. * The MDIO registers remain accessible.
3.4.3.3 Sleep Mode
The LXT971A supports a power-saving sleep mode. Sleep mode is enabled when SLEEP is asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by Register bit 16.6 when in managed mode as shown in Table 4 on page 18. The LXT971A enters into sleep mode when SLEEP is enabled and no energy is detected on the twisted-pair input for 1-3 seconds (the time is controlled by Register bits 16.4:3 in the Configuration Register, with a default of 3.04 seconds). During this mode, the LXT971A still responds to management transactions (MDC/MDIO). In this mode the power consumption is minimized, and the supply current is reduced below the maximum value given in Table 18 on page 56. If the LXT971A detects activity on the twisted-pair inputs, it comes out of the sleep state and check for link. If no link is detected in 1-3 seconds (programmable) it reverts back to the low power sleep state. Note: Sleep Mode is not functional in fiber network applications.
3.4.4
Reset
The LXT971A provides both hardware and software resets. Configuration control of autonegotiation, speed, and duplex mode selection is handled differently for each. During a hardware reset, auto-negotiation and speed configuration settings are read in from pins (refer to Table 9 on page 30 for pin settings and to Table 43 on page 74 for register bit definitions). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset is not detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0).
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3.4.5
Hardware Configuration Settings
The LXT971A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in Table 9. The LED drivers can operate as either open-drain or open-source circuits as shown in Figure 8.
Figure 8. Hardware Configuration Settings
3.3 V
Configuration Bit = 1 LED/CFG Pin
LED/CFG Pin Configuration Bit = 0
1. The LED/CFG pins automatically adjust their polarity upon power-up or reset. 2. Unused LEDs may be implemented with pull-up/ pull-down resistors of 10 K.
Table 9.
Hardware Configuration Settings
Desired Mode LED/CFGn Pin Settings1 Resulting Register Bit Values Control Register AutoNeg 0.12 Speed 0.13 FD 0.8 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 N/A Auto-Negotiation Advertisement AN Advertisement Registers 100FD 4.8 100TX 4.7 10FD 4.6 10T 4.5
AutoNeg
Speed (Mbps)
Duplex Half Full Half Full Half Full Half Only Full or Half
1 Low Low Low Low High High High High
2 Low Low High High Low Low High High
3 Low High Low High Low High Low High
10 Disabled 100 100 Only Enabled 10/100
0 0 1
1. Refer to Table 7 on page 19 for LED/CFG pin assignments.
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3.5
Establishing Link
See Figure 9 for an overview of link establishment.
3.5.1
Auto-Negotiation
If not configured for forced operation, the LXT971A attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of up to 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "link code word". All devices that support auto-negotiation must implement the "Base Page" defined by IEEE 802.3 (registers 4 and 5). LXT971A also supports the optional "Next Page" function as described in Tables 50 and 51 on page 80 (registers 7 and 8).
3.5.1.1
Base Page Exchange
By exchanging Base Pages, the LXT971A and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to continue. Each side identifies the highest common capabilities that both sides support and configures itself accordingly.
3.5.1.2
Next Page Exchange
Additional information, above that required by base page exchange is also sent via "Next Pages". The LXT971A fully supports the IEEE 802.3ab method of negotiation via Next Page exchange.
3.5.1.3
Controlling Auto-Negotiation
When auto-negotiation is controlled by software, the following steps are recommended:
* After power-up, power-down, or reset, the power-down recovery time, as specified in Table 40
on page 70, must be exhausted before proceeding.
* Set the Auto-Negotiation Advertisement Register bits. * Enable auto-negotiation (set MDIO Register bit 0.12 = 1). 3.5.2 Parallel Detection
For the parallel detection feature of auto-negotiation, the LXT971A also monitors for 10BASE-T Normal Link Pulses (NLP) and 100BASE-TX Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT971A to communicate with devices that do not support auto-negotiation.
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Figure 9. Link Establishment Overview
Power-Up, Reset, Waking up from Sleep mode, or Link Failure
Start Disable Auto-Negotiation 0.12 = 0
Check Value 0.12
0.12 = 1
Enable Auto-Neg/Parallel Detection
Go To Forced Settings
Attempt AutoNegotiation
Listen for 100TX Idle Symbols
Listen for 10T Link Pulses
Done
YES
Link Up?
NO
3.6
MII Operation
The LXT971A device implements the Media Independent Interface (MII) as defined in the IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC to the LXT971A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER, COL, and CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK, TX_EN, and TX_ER. The LXT971A supplies both clock signals as well as separate outputs for carrier sense and collision. Data transmission across the MII is normally implemented in 4-bit-wide nibbles.
3.6.1
MII Clocks
The LXT971A is the master clock source for data transmission and supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When the link is operating at 100 Mbps, the clocks are set to 25 MHz. When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz. Figures 10 through 12 show the clock cycles for each mode. The transmit data and control signals must always be synchronized to TX_CLK by the MAC. The LXT971A samples these signals on the rising edge of TX_CLK.
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3.6.2
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet.
3.6.3
Receive Data Valid
The LXT971A asserts RX_DV when it receives a valid packet. Timing changes depend on line operating speed:
* For 100BASE-TX links, RX_DV is asserted from the first nibble of preamble to the last nibble
of the data packet.
* For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of the
Start of Frame Delimiter (SFD) "5D" and remains asserted until the end of the packet.
3.6.4
Carrier Sense
Carrier Sense (CRS) is an asynchronous output. It is always generated when a packet is received from the line and in half-duplex mode when a packet is transmitted. Table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.
3.6.5
Error Signals
When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives "1110" on the RXD pins. When the MAC asserts TX_ER, the LXT971A drives "H" symbols out on the TPFOP/N pins.
3.6.6
Collision
The LXT971A asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. Table 10 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
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Figure 10. 10BASE-T Clocking
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT971A)
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 11. 100BASE-X Clocking
2.5 MHz during auto-negotiation 25 MHz once 100BASE-X Link Established
TX_CLK
(Sourced by LXT971A)
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X Link Established
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 12. Link Down Clock Transition
Link-Down Condition/Auto-Negotiate Enabled RX_CLK TX_CLK Any Clock 2.5 MHz Clock
Clock transition time will not exceed 2X the nominal clock period: 10 Mbps = 2.5 MHz 100 Mbps = 25 MHz
3.6.7
Loopback
The LXT971A provides two loopback functions, operational and test (see Table 10). Loopback paths are shown in Figure 13.
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3.6.7.1
Operational Loopback
Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16.8 = 0. Data transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16.8 = 1.
3.6.7.2
Test Loopback
A test loopback function is provided for diagnostic testing of the LXT971A. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT971A and returned to the MAC. Test loopback is available for both 100BASE-TX and 10BASE-T operation, and is enabled by setting the following register bits:
* Register bit 0.14 = 1 * Register bit 0.8 = 1 (full-duplex) * Register bit 0.12 = 0 (disable auto-negotiation).
Test loopback is also available for 100BASE-FX operation. Test loopback in this mode is enabled by setting Register bit 0.14 = 1 and tying the SD input to an LVPECL logic High value (2.4 V). Figure 13. Loopback Paths
LXT971A
FX Driver
MII
10T Loopback
Digital Block
100X Loopback
Analog Block
TX Driver
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Table 10. Carrier Sense, Loopback, and Collision Conditions
Speed Duplex Condition Carrier Sense Test1 Loopback Operational Loopback Collision
100 Mbps
Full-Duplex Half-Duplex Full-Duplex
Receive Only Transmit or Receive Receive Only Transmit or Receive Transmit or Receive
Yes No Yes Yes No
No No No Yes No
None Transmit and Receive None Transmit and Receive Transmit and Receive
10 Mbps
Half-Duplex, Register bit 16.8 = 0 Half-Duplex, Register bit 16.8 = 1
1. Test Loopback is enabled when 0.14 = 1
3.7
3.7.1
100 Mbps Operation
100BASE-X Network Operations
During 100BASE-X operation, the LXT971A transmits and receives 5-bit symbols across the network link. Figure 14 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT971A sends out Idle symbols on the line. In 100BASE-TX mode, the LXT971A scrambles and transmits the data to the network using MLT3 line code (Figure 15 on page 37). MLT-3 signals received from the network are de-scrambled, decoded, and sent across the MII to the MAC. In 100BASE-FX mode, the LXT971A transmits and receives NRZI signals across the LVPECL interface. An external 100FX transceiver module is required to complete the fiber connection. To enable 100BASE-FX operation, auto-negotiation must be disabled and FX selected.
Figure 14. 100BASE-X Frame Format
64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (Pad to minimum packet size) (4 Octets) (> 12 Octets)
P0
P1
P6
SFD
DA
DA
SA
SA
L1
L2
D0
D1
Dn
CRC
I0
IFG
Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD)
Start-of-Frame Delimiter (SFD)
Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD)
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Figure 15. 100BASE-TX Data Path
Standard Data Flow D0 D1 D2 D3
Parallel to Serial
+1 0 0 -1 0
Scramble
D0 D1 D2 D3
Serial to Parallel
4B/5B
S0
S1
S2
S3
S4
DeScramble
MLT3
Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow S0 S1 S2 S3 S4
Serial to Parallel Parallel to Serial
+1 0 0 -1 0
S0
S1
S2
S3
S4
MLT3
Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1...
As shown in Figure 14 on page 36, the MAC starts each transmission with a preamble pattern. As soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC. Once the packet ends, the LXT971A transmits the End-of- Stream Delimiter (ESD, symbols T and R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in Table 11 on page 40. Figure 16 shows normal reception with no errors. When the LXT971A receives invalid symbols from the line, it asserts RX_ER as shown in Figure 17. Figure 16. 100BASE-TX Reception with No Errors
RX_CLK
RX_DV
RXD<3:0>
preamble SFD SFD
DA
DA
DA
DA
CRC
CRC
CRC
CRC
RX_ER
Figure 17. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
RXD<3:0>
preamble SFD SFD
DA
DA
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
RX_ER
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3.7.2
Collision Indication
Figure 18 shows normal transmission. Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 19.
Figure 18. 100BASE-TX Transmission with No Errors
TX_CLK TX_EN TXD<3:0> CRS COL P R E A M B L E DA DA DA DA DA DA DA DA DA
Figure 19. 100BASE-TX Transmission with Collision
TX_CLK TX_EN TXD<3:0> CRS COL P R E A M B L E JAM JAM JAM JAM
3.7.3
100BASE-X Protocol Sublayer Operations
With respect to the 7-layer communications model, the LXT971A is a Physical Layer 1 (PHY) device. The LXT971A implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u standard. The following paragraphs discuss LXT971A operation from the reference model point of view.
3.7.3.1
PCS Sublayer
The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted.
3.7.3.1.1
Preamble Handling
When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start-ofStream Delimiter (SSD), for the first two nibbles received across the MII. The PCS layer continues to encode the remaining MII data, following the coding in Table 11, until TX_EN is de-asserted. It then returns to supplying IDLE symbols to the line driver.
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In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD.
3.7.3.1.2
Dribble Bits
The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, and padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. Figure 20. Protocol Sublayers
MII Interface PCS Sublayer LXT971A
Encoder/Decoder Serializer/De-serializer
PMA Sublayer
Link/Carrier Detect
PMD Sublayer
PECL Interface
Scrambler/ De-scrambler Fiber Transceiver
100BASE-TX
100BASE-FX
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Table 11. 4B/5B Coding
Code Type 4B Code 3210 Name 5B Code 43210 Interpretation
0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 IDLE undefined 0101 0101 CONTROL undefined undefined 1. 2. 3. 4.
0 1 2 3 4 5 6 7 8 9 A B C D E F I
1
11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 1 1 1 11 11000 10001 01101 00111
Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Used as inter-stream fill code Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2
J2 K2 T3 R3
The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition.
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Table 11. 4B/5B Coding (Continued)
Code Type 4B Code 3210 Name 5B Code 43210 Interpretation
undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined 1. 2. 3. 4.
H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition.
3.7.3.2
PMA Sublayer 3.7.3.2.1 Link
In 100 Mbps mode, the LXT971A establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. Whenever the scrambler loses lock (receiving less than 12 consecutive idle symbols during a 2 ms window), the link is taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. Furthermore, 100 Mbps idle patterns will not bring up a 10 Mbps link. The LXT971A reports link failure via the MII status bits (Register bits 1.2 and 17.10) and interrupt functions. Link failure causes the LXT971A to re-negotiate if auto-negotiation is enabled.
3.7.3.2.2
Link Failure Override
The LXT971A normally transmits data packets only if it detects the link is up. Setting Register bit 16.14 = 1 overrides this function, allowing the LXT971A to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT971A automatically transmits FLP bursts if the link is down.
3.7.3.2.3
Carrier Sense
For 100BASE-TX and 100FX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes deassertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R; however, in this case RX_ER is asserted for one clock cycle when CRS is de-asserted. Usage of CRS for Interframe Gap (IFG) timing is not recommended for the following reasons:
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* De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to
appear somewhat shorter to the MAC than it actually is on the wire. duplex mode.
* CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half3.7.3.2.4 Receive Data Valid
The LXT971A asserts RX_DV to indicate that the received data maps to valid symbols. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller.
3.7.3.3
Twisted-Pair PMD Sublayer
The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100BASE-TX, Manchester for 10BASE-T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/De-scrambler The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, data-independent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. Scrambler Seeding Once the transmit data (or Idle symbols) are properly encoded, they are scrambled to further reduce EMI and to spread the power spectrum using an 11-bit scrambler seed. Five seed bits are determined by the PHY address, and the remaining bits are hard coded in the design. Scrambler Bypass The scrambler/de-scrambler can be bypassed by setting Register bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic and test support.
3.7.3.3.1
Baseline Wander Correction
The LXT971A provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". This means that the average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. Exact characteristics of the wander are completely data dependent. The LXT971A baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths.
3.7.3.3.2
Polarity Correction
The 100BASE-TX de-scrambler automatically detects and corrects for the condition where the receive signal at TPFIP and TPFIN is inverted.
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3.7.3.3.3
Programmable Slew Rate Control
The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. This allows the designer to optimize the output waveform to match the characteristics of the magnetics. The slew rate is determined by the TxSLEW pins as shown in Table 4 on page 18.
3.7.3.4
Fiber PMD Sublayer
The LXT971A provides a Low Voltage PECL interface for connection to an external 3.3 V or 5.0 V fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT971A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications.
3.8
10 Mbps Operation
The LXT971A operates as a standard 10BASE-T transceiver. The LXT971A supports all the standard 10 Mbps functions. During 10BASE-T operation, the LXT971A transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT971A drives link pulses onto the line. In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT971A and sent across the MII to the MAC. The LXT971A does not support fiber connections at 10 Mbps.
3.8.1
10BASE-T Preamble Handling
The LXT971A offers two options for preamble handling, selected by Register bit 16.5. In 10BASE-T Mode when 16.5 = 0, the LXT971A strips the entire preamble off of received packets. CRS is asserted coincident with SFD. RX_DV is held Low for the duration of the preamble. When RX_DV is asserted, the very first two nibbles driven by the LXT971A are the SFD "5D" hex followed by the body of the packet. In 10BASE-T mode with 16.5 = 1, the LXT971A passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10BASE-T loopback, the LXT971A loops back whatever the MAC transmits to it, including the preamble.
3.8.2
10BASE-T Carrier Sense
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. Register bit 16.7 allows CRS de-assertion to be synchronized with RX_DV de-assertion. Refer to Table 52 on page 81.
3.8.3
10BASE-T Dribble Bits
The LXT971A device handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus.
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3.8.4
10BASE-T Link Integrity Test
In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test function is enabled (the normal configuration), it monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled and remains enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission is disabled. If the Link Integrity Test function is disabled, the LXT971A transmits to the connection regardless of detected link pulses. The Link Integrity Test function can be disabled by setting Register bit 16.14 = 1.
3.8.4.1
Link Failure
Link failure occurs if the Link Integrity Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT971A returns to the auto-negotiation phase if autonegotiation is enabled. If the Link Integrity Test function is disabled by setting Register bit 16.14 = 1 in the Configuration Register, the LXT971A transmits packets, regardless of link status.
3.8.5
10BASE-T SQE (Heartbeat)
By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A. To enable this function, set Register bit 16.9 = 1. When this function is enabled, the LXT971A asserts its COL output for 5-15 BT after each packet. See Figure 35 on page 67 for SQE timing parameters.
3.8.6
10BASE-T Jabber
If a transmission exceeds the jabber timer, the LXT971A disables the transmit and loopback functions. See Figure 34 on page 67 for jabber timing parameters. The LXT971A automatically exits jabber mode after the unjabber time has expired. This function can be disabled by setting Register bit 16.10 = 1.
3.8.7
10BASE-T Polarity Correction
The LXT971A automatically detects and corrects for the condition where the receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
3.9
3.9.1
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
* Register bit 17.7 is set to 1 once the auto-negotiation process is completed. * Register bits 1.2 and 17.10 are set to 1 once the link is established.
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* Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and
duplex).
3.9.1.1
Monitoring Next Page Exchange
The LXT971A offers an Alternate Next Page mode to simplify the next page exchange process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next Page mode is enabled Register bit 6.1 is automatically cleared whenever a new negotiation process takes place. This prevents the user from reading an old value in 6.1 and assuming that Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT971A uses Register bit 6.5 to indicate when the current received page is the base page. This information is useful for recognizing when next pages must be resent due to a new negotiation process starting. Register bits 6.1 and 6.5 are cleared when read.
3.9.2
LED Functions
The LXT971A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to Table 56 on page 85) to indicate one of the following conditions:
* * * * * *
Operating Speed Transmit Activity Receive Activity Collision Condition Link Status Duplex Mode
The LED drivers can also be programmed to display various combined status conditions. For example, setting Register bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:
* If Link is down LED is off. * If Link is up LED is on. * If Link is up and activity is detected, the LED blinks at the stretch interval selected by Register
bits 20.3:2 and continues to blink as long as activity is present. The LED driver pins also provide initial configuration settings. The LED pins are sensitive to polarity and automatically pull up or pull down to configure for either open drain or open collector circuits (10 mA Max current rating) as required by the hardware configuration. Refer to the discussion of "Hardware Configuration Settings" on page 30 for details.
3.9.2.1
LED Pulse Stretching
The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. The pulse stretch time is further extended if the event occurs again during this pulse stretch period. When an event such as receiving a packet occurs it is edge detected and it starts the stretch timer. The LED driver remains asserted until the stretch timer expires. If another event occurs before the stretch timer expires then the stretch timer is reset and the stretch time is extended.
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When a long event (such as duplex status) occurs it is edge detected and it starts the stretch timer. When the stretch timer expires the edge detector is reset so that a long event causes another pulse to be generated from the edge detector which resets the stretch timer and causes the LED driver to remain asserted. Figure 21 shows how the stretch operation functions. Figure 21. LED Pulse Stretching
Event
LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active Low.
3.10
Boundary Scan (JTAG1149.1) Functions
LXT971A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. The BSDL file is available by contacting your local sales office or by accessing the Intel website (www.intel.com).
3.10.1
Boundary Scan Interface
This interface consists of five pins (TMS, TDI, TDO, TRST, and TCK). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is internally pulled down. TDO does not have an internal pull-up or pull-down.
3.10.2
State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS pins. Upon reset the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are high for five TCK periods.
3.10.3
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in Table 13.
3.10.4
Boundary Scan Register (BSR)
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 12.
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Table 12. BSR Mode of Operation
Mode Description
1 2 3 4
Capture Shift Update System Function
Table 13. Supported JTAG Instructions
Name Code Description Mode Data Register
EXTEST IDCODE SAMPLE HIGHZ CLAMP BYPASS
1111 1111 1110 1000 1111 1111 1111 1110 1111 1111 1111 1000 1111 1111 1100 1111 1111 1111 1110 1111 1111 1111 1111 1111
External Test ID Code Inspection Sample Boundary Force Float Control Boundary to 1/0 Bypass Scan
Test Normal Normal Normal Test Normal
BSR ID REG BSR Bypass Bypass Bypass
Table 14. Device ID Register
31:28 Version2 27:12 Part ID (hex) 11:8 Jedec Continuation Characters 7:1 JEDEC ID1 0 Reserved
XXXX
03CB
0000
111 1110
1
1. The JEDEC IS is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110), which becomes 111 1110. 2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the Jedec continuation characters.
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4.0
4.1
Application Information
Magnetics Information
The LXT971A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 15 for transformer requirements. A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic Manufacturers for Networking Product Applications (document number 248991) and is found on the Intel web site (www.Intel.com). Before committing to a specific component, contact the manufacturer for current product specifications and validate the magnetics for the specific application.
Table 15. Magnetics Requirements
Parameter Min Nom Max Units Test Condition
Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection
- - 0.0 350 - 40 35 -16 -10
1:1 1:1 0.6 - 1.5 - - - -
- - 1.1 - - - - - -
- - dB
H
- - - - - .1 to 60 MHz 60 to 100 MHz 30 MHz 80 MHz
kV dB dB dB dB
Return Loss
4.2
Typical Twisted-Pair Interface
Table 16 provides a comparison of the RJ-45 connections for NIC and Switch applications in a typical twisted-pair interface setting.
Table 16. I/O Pin Comparison of NIC and Switch RJ-45 Setups
RJ-45 Symbol Switch NIC
TPIP TPIN TPOP TPON
1 2 3 6
3 6 1 2
Figure 22 on page 49 shows a typical twisted-pair interface with the RJ-45 connections crossed over for a Switch configuration. Figure 23 on page 50 provides a typical twisted-pair interface with the RJ-45 connections configured for a NIC application.
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Figure 22. Typical Twisted-Pair Interface - Switch
TPFIP
270 pF 5% RJ-45
1
0.01 F 50 1%
3
50 50
2 3 4
TPFIN TPFOP
270 pF 5% 1:1
50
5 6
LXT971A
TPFON
2
50 0.1F 50 50
7 8
1
*
*
* = 0.001 F / 2.0 kV
4
VCCA
0.1F .01F
GND SD/TP
1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center-tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT971A. 3. Magnetics without a receive pair center-tap do not require a 2 kV termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 23 on page 50.
Datasheet
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To Twisted-Pair Network
50 1%
1:1
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Figure 23. Typical Twisted-Pair Interface - NIC
RJ-45 270 pF 5% 50 50
8 7 6
50 1% 0.01 F 50 1%
1:1
3
50 50 50
5 4 3
TPFIP TPFON
270 pF 5% 1:1
2 1
LXT971A
TPFOP
2
0.1F
4 1
*
*
* = 0.001 F / 2.0 kV
VCCA
0.1F .01F
GND SD/TP
1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center-tap from a 2.5 V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 transmit load termination resistor typically required is integrated in the LXT971A. 3. Magnetics without a receive pair center-tap do not require a 2 kV termination. 4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and switch applications.
50
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TPFIN
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Figure 24. Typical MII Interface
TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK
MAC
RX_DV RX_ER RXD<3:0> CRS COL
LXT971A
X F M R
RJ-45
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4.3
The Fiber Interface
The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with the LXT971A. The following should occur in 3.3 V fiber transceiver applications as shown in Figure 25:
* The transmit pair should be DC-coupled with the 50 /16 pull-up combination * The receive pair should be DC-coupled with an emitter current path for the fiber transceiver * The signal detect pin should be DC-coupled with an emitter current path for the fiber
transceiver Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 25 shows a typical example of an LXT971A-to-3.3 V fiber transceiver interface. The following occurs in 5 V fiber transceiver applications as shown in Figure 26:
* The transmit pair should be AC-coupled and re-biased to 5 V PECL input levels * The receive pair should be AC-coupled with an emitter current path for the fiber transceiver
and re-biased to 3.3 V LVPECL input levels. The signal detect pin on a 5 V fiber transceiver interface should use the logic translator circuitry as shown in Figure 27. Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 26 shows a typical example of an LXT971A-to-5 V fiber transceiver interface, while Figure 27 shows the interface circuitry for the logic translator.
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Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry
+3.3V +3.3V
16
0.01F - 0.1 F
50 TPFON TPFOP
50 TD TD +
LXT971A
+3.3V
Fiber Txcvr
130 SD/TP 82
+3.3V
SD
0.01F - 0.1 F
1
130 130
TPFIN TPFIP 82 82
RD RD +
1. Refer to the transceiver manufacturer's recommendations for termination circuitry.
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Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry
+3.3V +3.3V +5V
16
0.01F - 0.1F 50 1.1k 0.01F 0.01F 1.1k
0.01F - 0.1F
50 TPFON TPFOP
TD TD + 3.1k 3.1k
LXT971A
Fiber Txcvr
2
SD/TP
ON Semiconductor MC100LVEL92 PECL-to-LVPECL Logic Translator
SD
+3.3V
0.01F - 0.1F
102
102
1
0.01F TPFIN TPFIP 154 154 270 270 0.01F
RD RD +
1. Refer to the transceiver manufacturer's recommendations for termination circuitry. 2. See Figure 27 for recommended logic translator interface circuitry.
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Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator
5V
0.01 F 0.01 F
5V
ON Semiconductor
3.3V 82 130
LVPECL Output Signal (LXT971A)
1 2
Vcc D0 __ D0 VBB PECL D1 __ D1 VBB PECL D2 __ D2 GND MC100LVEL92
Vcc Q0 __ Q0 LVCC
20 19 18 17
PECL Input Signal (5V Fiber Txcvr)
130
3 4 5 6 7 8 9 10
82
Q1 16 __ Q1 15 LVCC Q2 __ Q2
14 13 12
3.3V
3.3V 130
0.01 F
Vcc 11
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5.0
Note:
Test Specifications
Table 17 through Table 40 and Figure 28 through Figure 41 represent the performance specifications of the LXT971A. These specifications are guaranteed by test except where noted "by design." Minimum and maximum values listed in Table 19 through Table 40 apply over the recommended operating conditions specified in Table 18.
5.1
Electrical Parameters
Table 17. Absolute Maximum Ratings Parameter
Supply voltage LXT971A_C (Commercial) LXT971A_E (Extended)
Sym
VCC TOPA TOPA TST
Min
-0.3 -15 -55 -65
Max
4.0 +85 +100 +150
Units
V C C C
Operating temperature
Storage temperature
Caution:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 18. Operating Conditions
Parameter Sym Min Typ1 Max Units
Recommended operating temperature
LXT971A_C (Commercial) LXT971A_E (Extended) Analog & Digital I/O 100BASE-TX 10BASE-T 100BASE-FX
TOPA TOPA Vcca, Vccd Vccio ICC ICC ICC ICC ICC Icc ICC
0 -40 3.14 2.35 - - - - - - -
- - 3.3 - 92 66 72 40 - 51 90
70 85 3.45 3.45 110 82 95 45 1 - 110
C C V V mA mA mA mA mA mA mA
Recommended supply voltage2
VCC current
Sleep Mode Hard Power Down Soft Power Down Auto-Negotiation
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified.
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Table 19. Digital I/O Characteristics2
Parameter Symbol Min Typ1 Max Units Test Conditions
Input Low voltage Input High voltage Input current Output Low voltage Output High voltage
VIL VIH II VOL VOH
- 2.0 -10 - 2.4
- - - - -
0.8 - 10 0.4 -
V V
A
- - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA
V V
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Applies to all pins except MII, LED, XI/XO, and SD/TP pins. Refer to Table 20 for MII I/O Characteristics, Table 21 for XI/XO and Table 22 for LED Characteristics.
Table 20. Digital I/O Characteristics - MII Pins
Parameter Symbol Min Typ1 Max Units Test Conditions
Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Driver output resistance (Line driver output enabled)
VIL VIH II VOL VOH VOH RO
2
- 2.0 -10 - 2.2 2.0 - -
- - - - - - 100 100
0.8 - 10 0.4 - - - -
V V
A
- - 0.0 < VI < VCCIO IOL = 4 mA IOH = -4 mA, VCCIO = 3.3V IOH = -4 mA, VCCIO = 2.5V VCCIO = 2.5V VCCIO = 3.3V
V V V W W
RO2
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing.
Table 21. I/O Characteristics - REFCLK/XI and XO Pins
Parameter Symbol Min Typ1 Max Units Test Conditions
Input Low Voltage Input High Voltage Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance
2 2
VIL VIH
f
- 2.0 - 35 -
- - - - 3.0
0.8 -
V V ppm % pF
- - - - -
100
65 -
Tdc CIN
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing.
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Table 22. I/O Characteristics - LED/CFG Pins
Parameter Symbol Min Typ Max Units Test Conditions
Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage
VIL VIH II VOL VOH
- 2.0 -10 - 2.0
- - - - -
0.8 - 10 0.4 -
V V
A
- - 0 < VI < VCCIO IOL = 10 mA IOH = -10 mA
V V
Table 23. I/O Characteristics - SD/TP Pin
Parameter Sym Min Typ1 Max Units Test Conditions
Reset and Power-Up States - FX/TP Mode Configuration
Fiber Mode (Register bit 16.0 = 1) Twisted-Pair Mode (Register bit 16.0 = 0)
VFX VTP
600 -
1600-2400 GND
- 500
mV mV
- -
100BASE-FX Mode Normal Operation - SD Input from Fiber Transceiver
Input Low Voltage Input High Voltage
VIL VIH
1.49 2.14
1.6 2.4
1.83 2.42
V V
VCCD = 3.3 V VCCD = 3.3 V
1. Typical values are for design aid only; not guaranteed and not subject to production testing.
Table 24. 100BASE-TX Transceiver Characteristics
Parameter Symbol Min Typ1 Max Units Test Conditions
Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot Jitter (measured differentially)
VP Vss TRF TRFS DCD VOS -
0.95 98 3.0 - 35 - -
- - - - 50 - -
1.05 102 5.0 0.5 65 5 1.4
V % ns ns % % ns
Note 2 Note 2 Note 2 Note 2 Offset from 16 ns pulse width at 50% of pulse peak - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor.
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Table 25. 100BASE-FX Transceiver Characteristics
Parameter Symbol Min Typ1 Max Units Test Conditions
Transmitter
Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially)
VOP TRF -
0.6 - -
- - -
1.5 1.9 1.3
V ns ns
- 10 <-> 90% 2.0 pF load -
Receiver
Peak differential input voltage Common mode input range
VIP VCMIR
0.55 -
- -
1.5 VCC - 0.7
V V
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Table 26. 10BASE-T Transceiver Characteristics
Parameter Symbol Min Typ Max Units Test Conditions
Transmitter
Peak differential output voltage Transition timing jitter added by the MAU and PLS sections
VOP
2.2
2.5
2.8
V
With transformer, line replaced by 100 resistor After line model specified by IEEE 802.3 for 10BASE-T MAU
-
0
2
11
ns
Receiver
Receive Input Impedance Differential Squelch Threshold
ZIN VDS
- 300
- 420
22 585
k mV
- -
Table 27. 10BASE-T Link Integrity Timing Characteristics
Parameter Symbol Min Typ Max Units Test Conditions
Time Link Loss Receive Link Pulse Link Min Receive Timer Link Max Receive Timer Link Transmit Period Link Pulse Width
TLL TLP TLR MIN TLR MAX Tlt Tlpw
50 2 2 50 8 60
- - - - - -
150 7 7 150 24 150
ms Link Pulses ms ms ms ns
- - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Table 28. LXT971A Thermal Characteristics
Parameter LXT971ALC LXT971ALE LXT971ABE
Package Theta-JA Theta-JC Psi - JT
1 0x 10 x1.4 64 LD LQFP 58 C/W 27 C/W 3.4 C/W
10 x 10 x 1.4 64 LQFP 56 C/W 25 C/W 3.0 C/W
7 x 7 x .96 64 BGA-CSP 42 C/W 20 C/W -
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5.2
Timing Diagrams
Figure 28. 100BASE-TX Receive Timing - 4B Mode
0ns 250ns
TPFI t4 CRS t3 RX_DV t1 RXD<3:0> RX_CLK t6 t7 t2 t5
COL
Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode
Parameter Sym Min Typ1 Max Units2 Test Conditions
RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted
t1 t2 t3 t4 t5 t6 t7
10 10 3 12 10 16 17
- - - - - - -
- - 5 16 17 22 20
ns ns BT BT BT BT BT
- - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns.
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Figure 29. 100BASE-TX Transmit Timing - 4B Mode
0ns 250ns
TXCLK TX_EN
t1
t2 TXD<3:0> t5 TPFO t3 CRS
Table 30. 100BASE-TX Transmit Timing Parameters - 4B Mode
Parameter Symbol Min Typ1 Max Units2 Test Conditions
t4
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency)
t1 t2 t3 t4 t5
12 0 20 24 5.3
- - - - -
- - 24 28 5.7
ns ns BT BT BT
- - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns.
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Figure 30. 100BASE-FX Receive Timing
0ns 250ns
TPFI t4 CRS t3 RX_DV t1 RXD<3:0> RX_CLK t6 t7 t2 t5
COL
Table 31. 100BASE-FX Receive Timing Parameters
Parameter Sym Min Typ1 Max Units2 Test Conditions
RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of "J" to CRS asserted Receive start of "T" to CRS de-asserted Receive start of "J" to COL asserted Receive start of "T" to COL de-asserted
t1 t2 t3 t4 t5 t6 t7
10 10 3 12 16 10 14
- - - - - - -
- - 5 16 22 15 18
ns ns BT BT BT BT BT
- - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns.
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Figure 31. 100BASE-FX Transmit Timing
0ns 250ns
TXCLK TX_EN
t1
t2 TXD<3:0> t5 TPFO t3 CRS
Table 32. 100BASE-FX Transmit Timing Parameters
Parameter Symbol Min Typ1 Max Units2 Test Conditions
t4
TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency)
t1 t2 t3 t4 t5
12 0 17 22 5
- - - - -
- - 20 24 5.3
ns ns BT BT BT
- - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10-8 s or 10 ns.
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Figure 32. 10BASE-T Receive Timing
RX_CLK t3 RXD, RX_DV, RX_ER t1 t2
t4
t5
CRS t6 TPFI t9 COL t8 t7
Table 33. 10BASE-T Receive Timing Parameters
Parameter Sym Min Typ1 Max Units2 Test Conditions
RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPFIP/N in to RXD out (Rx latency) CRS asserted to RXD, RX_DV, RX_ER asserted RXD, RX_DV, RX_ER de-asserted to CRS de-asserted TPFI in to CRS asserted TPFI quiet to CRS de-asserted TPFI in to COL asserted TPFI quiet to COL de-asserted
t1 t2 t3 t4 t5 t6 t7 t8 t9
10 10 4.2 5 0.3 2 6 1 5
- - - - - - - - -
- - 6.6 32 0.5 28 10 31 10
ns ns BT BT BT BT BT BT BT
- - - - - - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-7 s or 100 ns.
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Figure 33. 10BASE-T Transmit Timing
TX_CLK t1 TXD, TX_EN, TX_ER t2
t3
t4
CRS t5 TPFO
Table 34. 10BASE-T Transmit Timing Parameters
Parameter Symbol Min Typ1 Max Units2 Test Conditions
TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted TX_EN sampled to TPFO out (Tx latency)
t1 t2 t3 t4 t5
10 0 - - -
- - 2 1 72.5
- - - - -
ns ns BT BT BT
- - - - -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. BT is the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10-7 s or 100 ns.
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Figure 34. 10BASE-T Jabber and Unjabber Timing
TX_EN t1 TXD
COL
t2
Table 35. 10BASE-T Jabber and Unjabber Timing Parameters
Parameter Symbol Min Typ1 Max Units Test Conditions
Maximum transmit time Unjab time
t1 t2
20 250
- -
150 750
ms ms
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
Figure 35. 10BASE-T SQE (Heartbeat) Timing
TX_CLK
TX_EN t1 COL t2
Table 36. 10BASE-T SQE Timing Parameters
Parameter Symbol Min Typ1 Max Units Test Conditions
COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration
t1 t2
0.65 0.5
- -
1.6 1.5
us us
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Figure 36. Auto-Negotiation and Fast Link Pulse Timing
Clock Pulse Data Pulse Clock Pulse
TPFOP
t1 t2 t1 t3
Figure 37. Fast Link Pulse Timing
FLP Burst FLP Burst
TPFOP
t4 t5
Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters
Parameter Symbol Min Typ1 Max Units Test Conditions
Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst
t1 t2 t3 t4 t5 -
- 55.5 123 - 8 17
100 - - 2 12 -
- 63.8 127 - 24 33
ns
s s
- - - - - -
ms ms ea
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Figure 38. MDIO Input Timing
MDC
t1 t2
MDIO
Figure 39. MDIO Output Timing
t4 MDC t3
MDIO
Table 38. MDIO Timing Parameters
Parameter Symbol Min Typ1 Max Units Test Conditions
MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source by PHY MDC period
t1 t2 t3 t4
10 5 - 125
- - - -
- - 150 -
ns ns ns ns
- - - MDC = 8 MHz
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
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Figure 40. Power-Up Timing
v1 VCC MDIO,etc t1
Table 39. Power-Up Timing Parameters
Parameter Symbol Min Typ1 Max Units Test Conditions
Voltage threshold Power Up delay2
v1 t1
- -
2.9 -
- 300
V
s
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance the PHY comes out of reset after a delay of No MORE Than 300 s. System designers should consider this as a minimum value - After threshold v1 is reached, the MAC should delay No LESS Than 300 s before accessing the MDIO port.
Figure 41. RESET Pulse Width and Recovery Timing
RESET
t1 t2
MDIO,etc
Table 40. RESET Pulse Width and Recovery Timing Parameters
Parameter Symbol Min Typ1 Max Units
Test Conditions
RESET pulse width RESET recovery delay2
t1 t2
10 -
-
- 300
ns
s
- -
1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Reset Recovery Delay is specified as a maximum value because it refers to the PHY guaranteed performance - the PHY comes out of reset after a delay of No MORE Than 300 s. System designers should consider this as a minimum value - After de-asserting RESET*, the MAC should delay No LESS Than 300 s before accessing the MDIO port.
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6.0
Register Definitions
The LXT971A register set includes multiple 16-bit registers. Table 41 presents a complete register listing. Table 42 is a complete memory map of all registers and Tables 43 through 58 provide individual register definitions. Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation" sections of the IEEE 802.3 standard. Additional registers are defined in accordance with the IEEE 802.3 standard for adding unique chip functions.
Table 41. Register Set
Address Register Name Bit Assignments
0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21-25 26 27-29 30
Control Register Status Register #1 PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Received Next Page Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Extended Status Register Port Configuration Register Status Register #2 Interrupt Enable Register Interrupt Status Register LED Configuration Register Reserved Digital Config Register Reserved Transmit Control Register
Refer to Table 43 on page 74 Refer to Table 44 on page 75 Refer to Table 45 on page 76 Refer to Table 46 on page 76 Refer to Table 47 on page 77 Refer to Table 48 on page 78 Refer to Table 49 on page 79 Refer to Table 50 on page 79 Refer to Table 51 on page 80 Not Implemented Not Implemented Not Implemented Refer to Table 52 on page 81 Refer to Table 53 on page 82 Refer to Table 54 on page 83 Refer to Table 55 on page 84 Refer to Table 56 on page 85 - Refer to Table 57 on page 86 - Refer to Table 58 on page 87
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Bit Fields B13 Control Register
Speed Select A/N Enable Isolate COL Test Reserved Power Down Re-start A/N Duplex Mode Speed Select
Table 42. Register Bit Map Addr
Reg Title B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B15
B14
Control Status Register
100BaseX Half Duplex Extended Status Reserved A/N Complete Remote Fault A/N Ability Link Status 10Mbps Full Duplex 10Mbps Half Duplex 100BaseT2 Full Duplex 100BaseT2 Half Duplex MF Preamble Suppress Jabber Detect
Reset
Loopbac k
0
Status PHY ID Registers
14 PHY ID No MFR Model No 13 12 11 10 9 8 7 6 5 4 3 2
100BaseT4
100BaseX Full Duplex
Extended Capabilit y
1
PHY ID 1
15
1 MFR Rev No
0
2 3
PHY ID2 Auto-Negotiation Advertisement Register
Remote Fault Reserved Pause Asymm Pause 100BaseT4 100BaseTX Full Duplex 100BaseTX 10Base-T 10Base-T Full Duplex
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
A/N Advertise
Next Page
Reserved
IEEE Selector Field
4
Auto-Negotiation Link Partner Base Page Ability Register
Ack Remote Fault Reserved Pause Asymm Pause 100BaseT4 100BaseTX Full Duplex 100BaseTX 10Base-T Full Duplex 10Base-T IEEE Selector Field
A/N Link Ability
Next Page
5
Auto-Negotiation Expansion Register
A/N Expansion
Reserved
Base Page
Parallel Detect Fault
Link Partner Next Page Able
Next Page Able
Page Received
Link Partner A/N Able
6
Auto-Negotiation Next Page Transmit Register
A/N Next Page Txmit
Message Page Ack 2 Toggle
Next Page
Reserved
Message / Unformatted Code Field
7
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Auto-Negotiation Link Partner Next Page Receive Register
Table 42. Register Bit Map (Continued)
Bit Fields B13
Message Page Ack 2 Toggle Message / Unformatted Code Field
Reg Title B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
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Datasheet Addr
8
B15
B14
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
A/N Link Next Page Configuration Register
Next Page
Ack
Port Config
Txmit Disable Reserved PRE_EN Sleep Timer Jabber (10T) Sleep Mode SQE (10T)
Reserved
Force Link Pass
Bypass Scrambler (100TX) CRS Select (10T) Fault Code Enable
TP Loopbac k (10T)
Alternate Next Page
Fiber Select
16
Status Register #2
Status Register #2
Transmit Status Link Reserved Polarity Pause Receive Status Collision Status Duplex Mode AutoNeg AutoNeg Complete Error
Reserved
10/100 Mode
Reserved
Reserved
17
Interrupt Enable Register
Reserved Reserved AutoNeg Mask Speed Mask Duplex Mask Link Mask Reserved Reserved Interrupt Enable Test Interrupt
Interrupt Enable Interrupt Status Register
Reserved Reserved AutoNeg Done Speed Change Duplex Change
18
Interrupt Status LED Configuration Register
LED1 LED2
Link Change
Reserved
MD Interrupt
Reserved
Reserved
19
LED Config
LED3
LED Freq
Pulse Stretch
Reserved
20
Digital Config Register (Address 26)
Reserved Increased MII Drive Strength
Digital Config
Reserved
Show Symbol Error
Reserved
26
Transmit Control Register
Port Rise Time Control Reserved Transmit Low Pwr
Trans. Control
Reserved
30
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
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Table 43. Control Register (Address 0)
Bit Name Description Type 1 Default
0.15 0.14
Reset Loopback
1 = PHY reset 0 = Normal operation 1 = Enable loopback mode 0 = Disable loopback mode 0.6 0.13 1 0 1 0 Speed Selected Reserved 1000 Mbps (not supported) 100 Mbps 10 Mbps
R/W SC R/W
0 0
0.13
Speed Selection
1 1 0 0
R/W
Note 2
0.12 0.11 0.10 0.9 0.8 0.7
Auto-Negotiation Enable Power-Down Isolate Restart Auto-Negotiation Duplex Mode Collision Test
1 = Enable auto-negotiation process 0 = Disable auto-negotiation process 1 = Power-down 0 = Normal operation 1 = Electrically isolate PHY from MII 0 = Normal operation 1 = Restart auto-negotiation process 0 = Normal operation 1 = Full-duplex 0 = Half-duplex 1 = Enable COL signal test 0 = Disable COL signal test 0.6 0.13 1 0 1 0 Speed Selected Reserved 1000 Mbps (not supported) 100 Mbps 10 Mbps
R/W R/W R/W R/W SC R/W R/W
Note 2 0 0 0 Note 2 0
0.6
Speed Selection
1 1 0 0
R/W
0
0.5:0
Reserved
Write as 0, ignore on Read
R/W
00000
1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFGn pins (refer to Table 9 on page 30).
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Table 44. MII Status Register #1 (Address 1)
Bit Name Description Type 1 Default
1.15 1.14 1.13
100BASE-T4 Not Supported 100BASE-X Full-Duplex 100BASE-X Half-Duplex
1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to operate at 10 Mbps in halfduplex 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform half-duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASET2 1 = Extended status information in register 15 0 = No extended status information in register 15 1 = ignore when read 1 = PHY accepts management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 1 = Auto-negotiation complete 0 = Auto-negotiation not complete 1 = Remote fault condition detected 0 = No remote fault condition detected 1 = PHY is able to perform auto-negotiation 0 = PHY is not able to perform auto-negotiation 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = Jabber condition not detected 1 = Extended register capabilities 0 = Basic register capabilities
RO RO RO
0 1 1
1.12
10 Mbps Full-Duplex
RO
1
1.11
10 Mbps Half-Duplex 100BASE-T2 FullDuplex Not Supported 100BASE-T2 HalfDuplex Not Supported
RO
1
1.10
RO
0
1.9
RO
0
1.8 1.7 1.6
Extended Status Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability
RO RO RO
0 0 0
1.5 1.4 1.3 1.2 1.1 1.0
RO RO/LH RO RO/LL RO/LH RO
0 0 1 0 0 1
1. RO = Read Only LL = Latching Low LH = Latching High
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Table 45. PHY Identification Register 1 (Address 2)
Bit Name Description Type 1 Default
2.15:0
PHY ID Number
The PHY identifier composed of bits 3 through 18 of the OUI.
RO
0013 hex
1. RO = Read Only
Table 46. PHY Identification Register 2 (Address 3)
Bit Name Description Type 1 Default
3.15:10 3.9:4
PHY ID number Manufacturer's model number Manufacturer's revision number
The PHY identifier composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number.
RO RO
011110 001110 xxxx (See the LXT971A/972A Specification Update)
3.3:0
4 bits containing manufacturer's revision number.
RO
1. RO = Read Only
Figure 42. PHY Identifier Bit Mapping
a
bc
Organizationally Unique Identifier
rs
x
PHY ID Register #1 (address 2) = 0013 15 0 15
PHY ID Register #2 (Address 3) 10 9 4 3 0
0000000000000100110111100011100000
00
20
7B
5
0
3
0
The Intel OUI is 00207B hex Manufacturer's Model Number Revision Number
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Table 47. Auto-Negotiation Advertisement Register (Address 4)
Bit Name Description Type 1 Default
4.15 4.14 4.13 4.12 4.11 4.10
Next Page Reserved Remote Fault Reserved Asymmetric Pause Pause
1 = Port has ability to send multiple pages. 0 = Port has no ability to send multiple pages. Ignore. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Pause operation enabled for full-duplex links. 0 = Pause operation disabled. 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available.
R/W RO R/W R/W R/W R/W
0 0 0 0 0 Note 2
4.9
100BASE-T4
(The LXT971A does not support 100BASE-T4 but allows this bit to be set to advertise in the autonegotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 1 = Port is 100BASE-TX full-duplex capable. 0 = Port is not 100BASE-TX full-duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T full-duplex capable. 0 = Port is not 10BASE-T full-duplex capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future auto-negotiation development. <11111> = Reserved for future auto-negotiation development. Unspecified or reserved combinations should not be transmitted.
R/W
0
4.8 4.7 4.6 4.5
100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T
R/W R/W R/W R/W
Note 3 Note 3 Note 3 Note 3
4.4:0
Selector Field, S<4:0>
R/W
00001
1. R/W = Read/Write RO = Read Only 2. The default setting of Register bit 4.10 (PAUSE) is determined by pin 33/H8 at reset. 3. Default values of Register bits 4.5, 4.6, 4.7, and 4.8 are determined by LED/CFGn pins at reset. Refer to Table 9 for details.
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Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)
Bit Name Description Type 1 Default
5.15
Next Page
1 = Link Partner has ability to send multiple pages. 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has received Link Code Word from LXT971A. 0 = Link Partner has not received Link Code Word from the LXT971A. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full-duplex capable. 0 = Link Partner is not 100BASE-TX full-duplex capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 100BASE-TX capable. 1 = Link Partner is 10BASE-T full-duplex capable. 0 = Link Partner is not 10BASE-T full-duplex capable. 1 = Link Partner is 10BASE-T capable. 0 = Link Partner is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future auto-negotiation development. <11111> = Reserved for future auto-negotiation development. Unspecified or reserved combinations shall not be transmitted.
RO
N/A
5.14
Acknowledge
RO
N/A
5.13 5.12 5.11
Remote Fault Reserved Asymmetric Pause Pause 100BASE-T4 100BASE-TX full-duplex 100BASE-TX 10BASE-T full-duplex 10BASE-T
RO RO RO
N/A N/A N/A
5.10 5.9 5.8 5.7 5.6 5.5
RO RO RO RO RO RO
N/A N/A N/A N/A N/A N/A
5.4:0
Selector Field S<4:0>
RO
N/A
1. RO = Read Only
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Table 49. Auto-Negotiation Expansion (Address 6)
Bit Name Description Type 1 Default
6.15:6
Reserved
Ignore on read. This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links. This bit is only used if Register bit 16.1 (Alternate NP feature) is set. 1 = Base page = true 0 = Base page = false
RO
0
6.5
Base Page
RO/ LH
0
6.4 6.3 6.2
Parallel Detection Fault Link Partner Next Page Able Next Page Able
1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred. 1 = Link partner is next page able. 0 = Link partner is not next page able. 1 = Local device is next page able. 0 = Local device is not next page able. 1 = Indicates that a new page has been received and the received code word has been loaded into Register 5 (Base Pages) or Register 8 (Next Pages) as specified in Clause 28 of IEEE 802.3. This bit is cleared on Read. If Register bit 16.1 is set, the Page Received bit is also cleared when mr_page_rx = false or transmit_disable = true. 1 = Link partner is auto-negotiation able. 0 = Link partner is not auto-negotiation able.
RO/ LH RO RO
0 0 1
6.1
Page Received
RO LH
0
6.0
Link Partner A/N Able
RO
0
1. RO = Read Only LH = Latching High
Table 50. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit Name Description Type 1 Default
7.15 7.14 7.13 7.12
Next Page (NP) Reserved Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/Unformatted Code Field
1 = Additional next pages follow 0 = Last page Write as 0, ignore on read 1 = Message page 0 = Unformatted page 1 = Complies with message 0 = Cannot comply with message 1 = Previous value of the transmitted Link Code Word equalled logic zero 0 = Previous value of the transmitted Link Code Word equalled logic one
R/W RO R/W R/W
0 0 1 0
7.11
R/W
0 00000000 001
7.10:0
R/W
1. RO = Read Only. R/W = Read/Write
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Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)
Bit Name Description Type 1 Default
8.15
Next Page (NP) Acknowledge (ACK)
1 = Link Partner has additional next pages to send 0 = Link Partner has no additional next pages to send 1 = Link Partner has received Link Code Word from LXT971A 0 = Link Partner has not received Link Code Word from LXT971A 1 = Page sent by the Link Partner is a Message Page 0 = Page sent by the Link Partner is an Unformatted Page 1 = Link Partner complies with the message 0 = Link Partner cannot comply with the message 1 = Previous value of the transmitted Link Code Word equalled logic zero 0 = Previous value of the transmitted Link Code Word equalled logic one RO 0
8.14
RO
0
8.13
Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/Unformatted Code Field
RO
0
8.12
RO
0
8.11
RO
0
8.10:0
User definable
RO
0
1. RO = Read Only.
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Table 52. Configuration Register (Address 16, Hex 10)
Bit Name Description Type 1 Default
16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8 16.7 16.6
Reserved Force Link Pass Transmit Disable Bypass Scrambler (100BASE-TX) Reserved Jabber (10BASE-T) SQE (10BASE-T) TP Loopback (10BASE-T) CRS Select (10BASE-T) Sleep Mode
Write as zero, ignore on read. 1 = Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter 0 = Normal Operation 1 = Bypass Scrambler and Descrambler 0 = Normal Operation Ignore 1 = Disable Jabber Correction 0 = Normal operation 1 = Enable Heart Beat 0 = Disable Heart Beat 1 = Disable TP loopback during half-duplex operation 0 = Normal Operation 1 = CRS deassert extends to RX_DV deassert 0 = Normal Operation 1 = Enable Sleep Mode 0 = Disable Sleep Mode Preamble Enable. 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD = preamble when CRS is asserted. 00 = 3.04 seconds 01 = 2.00 seconds 10 = 1.04 seconds 1 = Enable FEFI transmission 0 = Disable FEFI transmission 1 = Enable alternate auto negotiate next page feature. 0 = Disable alternate auto negotiate next page feature 1 = Select fiber mode. 0 = Select TP mode.
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 0 0 0 0 0 0 0 1 Note 2
16.5
PRE_EN
R/W
0
16.4:3
Sleep Timer Fault Code Enable Alternate NP feature Fiber Select
R/W
00
16.2
R/W
1
16.1
R/W
0
16.0
R/W
Note 3
1. R/W = Read /Write LHR = Latches High on Reset 2. The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7. 3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP).
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Table 53. Status Register #2 (Address 17)
Bit Name Description Type 1 Default
17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8
Reserved 10/100 Mode Transmit Status Receive Status Collision Status Link Duplex Mode Auto-Negotiation
Always 0. 1 = LXT971A is operating in 100BASE-TX mode. 0 = LXT971A is not operating 100BASE-TX mode. 1 = LXT971A is transmitting a packet. 0 = LXT971A is not transmitting a packet. 1 = LXT971A is receiving a packet. 0 = LXT971A is not receiving a packet. 1 = Collision is occurring. 0 = No collision. 1 = Link is up. 0 = Link is down. 1 = Full-duplex. 0 = Half-duplex. 1 = LXT971A is in auto-negotiation mode. 0 = LXT971A is in manual mode. 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. This bit is only valid when auto negotiate is enabled, and is equivalent to Register bit 1.5. Always 0. 1 = Polarity is reversed. 0 = Polarity is not reversed. 1 = Device Pause capable. 0 = Device Not Pause capable. 1 = Error Occurred (Remote Fault, X,Y, Z). 0 = No error occurred. Always 0. Always 0. Always 0.
RO RO RO RO RO RO RO RO
0 0 0 0 0 0 0 0
17.7
Auto-Negotiation Complete Reserved Polarity Pause Error Reserved Reserved Reserved
RO
0
17.6 17.5 17.4 17:3 17:2 17:1 17.0
RO RO RO RO RO RO RO
0 0 0 0 0 0 0
1. RO = Read Only. R/W = Read/Write
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Table 54. Interrupt Enable Register (Address 18)
Bit Name Description Type 1 Default
18.15:9 18.8 18.7
Reserved Reserved ANMSK
Write as 0; ignore on read. Write as 0; ignore on read. Mask for Auto Negotiate Complete 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Speed Interrupt 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Duplex Interrupt 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Link Status Interrupt 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Write as 0, ignore on read. Write as 0, ignore on read. 1 = Enable interrupts. 0 = Disable interrupts. 1 = Force interrupt on MDINT. 0 = Normal operation.
R/W R/W R/W
N/A 0 0
18.6
SPEEDMSK
R/W
0
18.5
DUPLEXMSK
R/W
0
18.4 18.3 18.2 18.1 18.0
LINKMSK Reserved Reserved INTEN TINT
R/W R/W R/W R/W
0 0 0 0
R/W
0
1. R/W = Read /Write
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Table 55. Interrupt Status Register (Address 19, Hex 13)
Bit Name Description Type 1 Default
19.15:9 19.8
Reserved Reserved
Ignore Ignore Auto-negotiation Status
RO RO
N/A 0
19.7
ANDONE
1= Auto-negotiation has completed. 0= Auto-negotiation has not completed. Speed Change Status 1 = A Speed Change has occurred since last reading this register. 0 = A Speed Change has not occurred since last reading this register. Duplex Change Status 1 = A Duplex Change has occurred since last reading this register. 0 = A Duplex Change has not occurred since last reading this register. Link Status Change Status 1 = A Link Change has occurred since last reading this register. 0 = A Link Change has not occurred since last reading this register.
RO/SC
N/A
19.6
SPEEDCHG
RO/SC
0
19.5
DUPLEXCHG
RO/SC
0
19.4
LINKCHG
RO/SC
0
19.3 19.2 19.1 19.0
Reserved MDINT Reserved Reserved
Ignore. 1 = MII interrupt pending. 0 = No MII interrupt pending. Ignore. Ignore
RO RO RO RO
0
N/A 0
1. R/W = Read/Write, RO = Read Only, SC = Self Clearing.
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Table 56. LED Configuration Register (Address 20, Hex 14)
Bit Name Description Type 1 Default
LED1 20.15:12 Programming bits
0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) 0100 = Display Link Status (Continuous) 0101 = Display Duplex Status (Continuous) 0110 = Unused 0111 = Display Receive or Transmit Activity (Stretched) 1000 = Test mode- turn LED on (Continuous) 1001 = Test mode- turn LED off (Continuous) 1010 = Test mode- blink LED fast (Continuous) 1011 = Test mode- blink LED slow (Continuous) 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status 0011 = Display Collision Status 0100 = Display Link Status (Default) 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused
R/W
0000
LED2 20.11:8 Programming bits
R/W
0100
1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are relative approximations. Not guaranteed or production tested.
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Table 56. LED Configuration Register (Address 20, Hex 14) (Continued)
Bit Name Description Type 1 Default
LED3 20.7:4 Programming bits
0000 = Display Speed Status 0001 = Display Transmit Status 0010 = Display Receive Status (Default) 0011 = Display Collision Status 0100 = Display Link Status 0101 = Display Duplex Status 0110 = Unused 0111 = Display Receive or Transmit Activity 1000 = Test mode- turn LED on 1001 = Test mode- turn LED off 1010 = Test mode- blink LED fast 1011 = Test mode- blink LED slow 1100 = Display Link and Receive Status combined 2 (Stretched)3 1101 = Display Link and Activity Status combined 2 (Stretched)3 1110 = Display Duplex and Collision Status combined 4 (Stretched)3 1111 = Unused 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 0 = Disable pulse stretching of all LEDs. 1 = Enable pulse stretching of all LEDs. Ignore.
R/W
0010
20.3:2
LEDFREQ5 PULSESTRETCH Reserved
R/W
00
20.1 20.0
R/W R/W
1 N/A
1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch Register bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full-duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Values are relative approximations. Not guaranteed or production tested.
Table 57. Digital Config Register (Address 26)
Bit Name Description Type 1 Default
26.15:12 26.11 26.10 26.9 26.8:0
Reserved MII Drive Strength Reserved Show Symbol Error Reserved
Reserved 1 = Increased MII drive strength 0 = Normal MII drive strength Reserved 1 = Map Symbol Error Signal To RXER 0 = Normal RXER Reserved
RO R/W RO R/W RO
0 0 0 0 0
1. R/W = Read /Write, RO = Read Only, LH = Latching High
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Table 58. Transmit Control Register (Address 30)
Bit Name Description Type2 Default
30.15:11 30.12
Reserved Transmit Low Power
Ignore 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission. 0 = Normal transmission. 00 = 3.0 ns (default = TXSLEW<1:0> pins) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns Ignore
R/W R/W
0 0
30.11:10 30.9:0
Port Rise Time Control Reserved
1
R/W R/W
00 0
1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write
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7.0
Package Specifications
Figure 43. PBGA Package Specification
64-Ball Plastic Ball Grid Array Package
* Part Number - LXT971ABC Commercial Temperature Range (0C to +70C) * Part Number - LXT971ABE Extended Temperature Range (-40C to +85C)
0.20 A 2.00 REF. 6.30 0.70 REF. 0.80 2.00 REF. OPTION: PIN A1 IDENTIFIER 1.00 0.10 INK OR LASER MARKING 7.00 0.20 (4X) 7.00 0.20 B
A B C D E F G
1.26 0.10 0.70 0.025 0.26 0.04 0.28 0.10
TOP VIEW
H 8 7 6 5 4 3 2 1
0.30 0.40 0.15 0.15 C C B A
2
BOTTOM VIEW C
SEATING PLANE SIDE VIEW
3
NOTES: 1. All dimensions and tolerances conform to ASME Y 14.5 M - 1994. 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C. 3. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 4. Maximum mold to substrate offset shall be 0.127. 5. The surface finish of the package shall be EDM Charmille #18 - #21. 6. Unless otherwise specified tolerance: Decimal 0.05 Angular 2.
88
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
www..com
Figure 44. LXT971A LQFP Package Specifications
64-Pin Low Profile Quad Flat Pack
* Part Number - LXT971ALC Commercial Temperature Range (0C to +70C) * Part Number - LXT971ALE Extended Temperature Range (-40C to +85C)
D D1
Millimeters Dim A A1 A2 B D D1 E E1 e L L1 Min - 0.05 1.35 0.17 11.85 9.9 11.85 9.9 0.45 11o 0o Max 1.60 0.15 1.45 0.27 12.15 10.1 12.15 10.1 0.75 13o 7o
E1
E
0.50 BSC1 1.00 REF
e e/ 2
3
1. Basic Spacing between Centers
A A1 L
L1
3 A2 B 3
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002
89
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
www..com
8.0
Product Ordering Information
Table 59. Product Information
Number Revision Qualification Tray MM Tape & Reel MM
DJLXT971ALC.A4 DJLXT971ALE.A4 FLLXT971ABC.A4 FLLXT971ABE.A4
A4 A4 A4 A4
S S S S
834105 835676 834103 834104
834916 835791 834926 835080
Figure 45. Ordering Information - Sample
DJ LXT 971A L C A4 S E001 Build Format E000 = Tray E001 = Tape and reel Qualification = Pre-production material Q = Production material S Product Revision = 2 Alphanumeric characters xn Temperature Range = Ambient (0 - 55 C) A = Commercial (0 - 70 C) C = Extended (-40 - +85 C) E Internal Package Designator = LQFP L = PLCC P = DIP N = PQFP Q = QFP with heat spreader H = TQFP T = BGA B = CBGA C = TBGA E = HSBGA (BGA with heat slug) K xxxx = 3-5 Digit Alphanumeric Product Code
IXA Product Prefix = PHY layer device LXT = Switching engine IXE = Formatting device (MAC) IXF = Network processor IXP Intel Package Designator DJ = LQFP FA = TQFP FL = PBGA (<1.0 mm pitch) FW = PBGA (1.27 mm pitch) HB = QFP with heat spreader HD = QFP with heat slug HF = CBGA HG = SOIC S = QFP GC = TBGA N = PLCC
90
Datasheet
Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002

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